1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device with a trench isolation, where the trench has a small width and a large depth. More particularly, the present invention relates to a method of fabricating a semiconductor device with a trench isolation suitable for fabricating a MOS transistor having a uniform threshold voltage.
2. Description of the Related Art
In recent years, an isolation structure by use of a narrow and deep trench, which is formed on a surface of a semiconductor substrate, and which is filled with an SiO.sub.2 film, or a stacked layer of an SiO.sub.2 film and a polycrystal silicon film, has been employed in a semiconductor device with progress in miniaturization of semiconductor devices.
A conventional method of fabricating a semiconductor device with a trench isolation will be described. FIG. 1A is a plan view showing a conventional method of fabricating a semiconductor device and FIG. 1B is a sectional view taken along line 1B--1B of FIG. 1. FIG. 2 is a sectional view showing a subsequent process step to the process step shown in FIGS. 1A and 1B. FIG. 3A is a plan view showing a further process step subsequent to that shown in FIG. 2 and FIG. 3B is a sectional view taken along line 2B--2B of FIG. 3A. In the conventional method of fabricating a semiconductor device, first a pad oxide film 22 format and a silicon nitride film 23 sequentially, for example, on a p-type silicon semiconductor substrate 21. As shown in FIGS. 1A and 1B a trench reaching the silicon semiconductor substrate 21 is formed by use of photolithographic technique, dry etching technique and the like. Thus a first active region 25a and a second active region 25b are divided.
As shown in FIG. 2, a first silicon oxide film 26 is formed by thermal oxidation in a region on a surface of the silicon semiconductor substrate 21 where a trench 24 is formed. The interior of the trench 24 is filled with a second silicon oxide film 27 by means of a CVD method. Subsequently the pad oxide film 22 and the silicon nitride film 23 in the first active region 25a or the second active region 25b are removed by a CMP (Chemical Mechanical Polishing) method or an etching-back method to flatten the surface.
As shown in FIGS. 3A and 3B, a gate oxide film 28 is formed on the surface of the silicon semiconductor substrate 21. A channel-doped layer 29 is formed by implanting ions of a p-type impurity such as boron or the like in a predetermined region where a channel of a MOS transistor is to be formed. Then a gate electrode 30 traversing the active regions 25a and 25b is formed on the channel-doped layer 29. An n-type impurity is ion-implanted in the active region 25a and 25b with the gate electrode as a mask and the active regions 25a and 25b receive a heat treatment, so that source/drain regions 31a and 31b are formed.
In a fabricated semiconductor device fabricated according to the above described method, a punch-through phenomenon between elements respectively fabricated in these regions is suppressed since the active regions 25a and 25b are isolated by the deep trench 24.
However, since a heat treatment is conducted after an impurity such as boron or the like is ion-implanted to form the channel-doped layer 29, the implanted impurity is diffused up to the second silicon oxide film 27. For that reason, the impurity concentration is not uniform at an end 29a of the channel-doped layer 29 on the side of the trench 24. FIG. 4 is a graph showing a relation between the gate voltage V.sub.G and the drain current I.sub.D of a semiconductor device fabricated by means of the conventional method with values of the gate voltage V.sub.G shown on the horizontal axis and values of the drain current I.sub.D shown on the vertical axis. The gate voltage V.sub.G vs. drain current I.sub.D characteristics of a semiconductor device fabricated by means of the conventional method are like superposition of the characteristics of two transistors of different kinds and an irregularity like a bump is observed on the curve as shown in FIG. 4. This irregularity is the result of the non-uniformity in threshold voltage as mentioned above.
There have been proposed methods of fabricating semiconductor devices each with a trench isolation (Japanese Unexamined Patent Publication Nos. Hei 1-155654 and Hei 2-23664). According to a conventional fabricating method described in Japanese Unexamined Patent Publication No. Hei 1-155654, a trench is formed on a silicon substrate. Thereafter a silicon oxide film is formed by a thermal oxidation method on the side wall portion and the bottom portion of the trench on the semiconductor substrate. Then ion implantation is carried out in the side wall portion and the bottom portion, and subsequently, a heat treatment is given there to further form a silicon oxide film. A semiconductor device fabricated by means of this fabrication method has a similar structure to the device as mentioned above.
On the other hand, according to a fabricating method described in Japanese Unexamined Patent Publication No. Hei 2-23664, in order to prevent a leakage in a trench capacitor or a trench gate, after a trench is formed on a semiconductor substrate, oxygen ions are implanted in the region on the semiconductor substrate where a trench is formed and the region is annealed. Thus an oxide film is formed and the region where the trench is formed comes to have an SOI structure.
Even in semiconductor devices fabricated by these methods, the problem that a threshold voltage is not uniform resulting in the observable irregularity on the gate voltage V.sub.G vs. drain current I.sub.D characteristics curve. There is another method, which is associated with Japanese Unexamined Patent Publication No. Hei 2-23664, in which nitrogen ions are implanted instead of oxygen ions and annealing is given, for example, in the range of 1000 to 1100.degree. C., but, since a silicon nitride buried layer is formed in a semiconductor device fabricated by means of the method, many crystal defects are present in the device and a leakage current is apt to occur.
Another method of fabricating a semiconductor device has further been proposed, though it is not related to a trench isolation, in which a film preventing a diffusion of an impurity is provided in order to prevent a punch-through phenomenon caused by a short channel effect (Japanese Unexamined Patent Publication No. Hei 3-66165). According to a method of fabricating a semiconductor device disclosed in the publication, oxygen or nitrogen ions, which are both low in thermal diffusion coefficient, are implanted in a boundary portion between a predetermined source/drain region and the bulk of a semiconductor substrate and an annealing treatment follows thereafter.
In the conventional fabricating method, since a region implanted with oxygen and nitrogen ions is already formed, phosphorus implanted in predetermined regions, where source/drain regions are to be formed, are mainly diffused in a horizontal direction by annealing.
However, even if this method is applied to a trench isolation in a device, a threshold voltage is not sufficiently uniform.